Different types of digital computer architecture

Von Neumann Architecture, Harvard Architecture and Modified Harvard Architecture

Von Neumann Architecture
also known as Princeton Architecture.
THE FUNDAMENTAL THING ABOUT THIS ARCHITECTURE IS THAT IT HAS SAME PROGRAM AND DATA MEMORY.
 Everything is stored in the memory and we can't be sure the bytes located in memory is either code or data until we execute it. Only during the execution phase, the distinction is made and the instruction decoder determines whether the given set of bits are to be used as data or code.
The design however will be simple as only one set of address lines will suffice to address both code and data(as the memory is same here). The size of the word width, timing, implementation and memory address is same for both the code and data so the overall processor architecture is simple.
The code here can be accessed and treated as the data and vice versa. This allows the code to be read from the disk storage and executed as code.
The basic structure
    a memory, containing instructions and data
    a processing unit, for performing arithmetic and logical operations
    a control unit, for interpreting instructions
    an input/output unit, for interacting with input and output devices
The execution cycle
    Fetch-Decode-Execute cycle

1. The first cycle in Neumann Architecture is to fetch the instructions with the aid of the Program Counter to determine the location of the instructions.
2. The instructions is decoded using Instruction Decoder so that the CPU can understand and implement the instructions meant for it.
3. Then, depending upon the type of instructions, it is determined whether data have to be fetched if so data is fetched from the memory and stored in the registers.
4. The code is executed and the result is stored in the registers or memory depending on the type of instructions.

Drawbacks:

1.  Von Neumann Bottleneck(discussed later)
2.   Program Modification -  Sometimes we end up modifying the code whether intentionally or by oversight but this will be detrimental and the system may crash.
3.  A malfunctioning program can damage itself, other programs or the operating system possibly leading to the computer crash.                 Solution: This kind of problem can however be solved using memory protection and access control. The program are restricted to stay or hover around in its address space and cannot access or modify the address space of other programs.

Von Neumaan Bottleneck
This problem arises as a result of the shared bus between the program and data memory. Due to this sharing, the program and data memory cannot be accessed in the same time as a result of which CPU's throughput is much smaller.
eg: in the instructions where we have to fetch two data from the memory, add it and store it back, the following sequences take place
    1. instruction fetch (CPU is idle during this period)
    2. Instruction decode
    3. First Data is fetched (CPU is idle during this period)
    4. Second Data is fetched (CPU is idle during this period)
    5. Addition operation is performed
    6. Result is stored back (CPU is idle during this period)
As we can see most of the time, CPU remains idle waiting for the program or data to be fetched and thus it reduces the throughput tremendously.

Harvard Architecture

IT HAS PHYSICALLY SEPERATE STORAGE AND SIGNAL PATHWAYS FOR INSTRUCTIONS AND DATA.
Memory:
    There is no need to make the two memories share characteristics like the        word width , timing implementations and memory address structure.
 eg: Instructions can be stored in ROM while data memory can be stroed in          Read-Write memory.
 Similarly,for the architecuture where instructions are more than data, we can have wider instruction address while the data address can be narrower.

Due to the previlige of having both instructions and data, we can concurrently run the instruction fetch and data fetch in the Harvard Architecture even without cache. This can tremendously increase the throughput as we can decrease the idle time the CPU spent in fetching the data or instructions.
However, pure Harvard Architecture itself will be quite complicated as the number of pins will be large compared to that of Von Neumaan. Furthermore, the memory characteristics can be different for the data and instructions so they should be handled seperately.
The circuit complexity is the price we have to pay for the faster execution.
 Furthermore, it can be costly to maintain to seperate two different memories altogether. Like, we have to have a seperate memory for our operating systems and all the codes and in the same time we have to maintain a memory for our data. So, the notions of the modern PCs where we have a single disc to store all our codes and data cannot be followed in the strict sense. This led to rise of the Modified Harvard Architecture.
example of processor using pure Harvard Architecture are
-Digital Signal Processors
-Microcontrollers

Modified Harvard Architecture

It fundamentally tries to bridge the gap between the two architectures disscussed above while trying to ameliorate the performance of the CPU. It is more or less a Harvard Architecture but is more lenient in the strict seperation between instruction and data. However, it allows CPU to concurrently access two memory buses( code and instructions). The common modification includes the seperate instructions and data caches with the common address space. Here, basically we will be having both the instructions and data buses but the address space donot overlap with each other as in the Harvard Architecture. Furthemore, it will be having a single main memory and the disk beyond the cache. Thus,
    -when executing from the cache it behaves like the pure Harvard
    -when accessing backing memory, however, it acts like a Von Neumaan
example:
    -ARM architecture
    -x86 processors
   
Comparitsions between Von Neumaan, Harvard and Modified Harvard Architecture
>Address space of instrucion and data memories
    eg: 0 instruction address space is totally different then 0 address space for data in Harvard Architecture
        However, Von Neumaan and Modified Harvard share both data and instructions in a single address space. Like the 0 address             space can contain data of memory in this case.
>Seperate Hardware Pathways to the CPU for the data and instructions memories
    Harvard and Modified Harvard have it.
    Von Neumaan doesn't have it.
>Different ways to access Instructions and data memories
    Harvard has this feature
    Von Neumaan and Modified Harvard don't have it.